Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a flash memory device including a plurality of memory cells.
In general, a semiconductor memory device is classified into a volatile memory device, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), and a non-volatile memory device, such as a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM) or a flash memory device. The biggest difference between the volatile memory device and the non-volatile memory device lies in whether data stored in a memory cell is preserved after a predetermined time passes. In the volatile memory device, the data stored in the memory cell is not preserved after the predetermined time passes. Meanwhile, in the non-volatile memory device, the data stored in the memory cell is preserved after the predetermined time passes. In this regard, the volatile memory device necessarily requires a refresh operation in order to preserve data. Meanwhile, the non-volatile memory device does not require the refresh operation. Since the non-volatile memory device is suitable for low power consumption and high integration, it has been extensively used as a data storage medium.
A flash memory device of the non-volatile memory device includes a plurality of memory cells for storing data, and the plurality of memory cells are serially coupled to one another to form one cell string.
In general, a flash memory device performs a program operation and an erase operation to store data in the memory cells. According to the program operation, electrons are accumulated in a floating gate of a transistor constituting a memory cell. According to the erase operation, the electrons accumulated in the floating gate are discharged to a substrate. The flash memory device stores data of ‘0’ or ‘1’ in the memory cell through the program operation and the erase operation, and senses the amount of the electrons accumulated in the floating gate at the time of a reading operation to determine data of ‘0’ or ‘1’ according to the sensing result.
As described above, data of ‘0’ or ‘1’ is stored in one memory cell. Because one bit data is stored in one memory cell, the memory cell is called a single level cell. Recently, memory cells which can store one or more bits of data have been developed. Such a memory cell is called a multi-level cell. The single level cell uses a single threshold voltage in order to determine data of ‘0’ or ‘1’ stored in the memory cell. On the other hand, the multi-level cell uses multiple threshold voltages in order to determine data (e.g., data of ‘00’, ‘01’, ‘10’ and ‘11’) stored in the memory cell.
FIG. 1 is a diagram illustrating the configuration of a general flash memory device.
Referring to FIG. 1, the flash memory device includes a memory cell block 110 having a plurality of cell strings ST, a source line driving unit 120, a page buffer 130, and an NMOS transistor NM. The source line driving unit 120 drives a common source line CSL by using a power supply voltage VDD or a ground supply voltage VSS according to an operation mode. The page buffer 130 performs a precharging operation and a data sensing operation with respect to a corresponding bit line BL. The NMOS transistor NM couples a bit line BL to the page buffer 130 in response to a bit line selection signal BL_SEL.
In general, the flash memory device applies a programming voltage to a plurality of word lines WL0 to WLn, thereby storing desired data in a corresponding memory cell. The programming voltage applied to the word lines WL0 to WLn is applied using an incremental step pulse program (ISPP) method. According to the ISPP method, a predetermined primary programming voltage is applied to a word line selected at the time of a program operation, and then a secondary programming voltage higher than the primary programming voltage is applied. More specifically, the ISPP method uses a stepped voltage level to adjust the programming voltage.
The program operation is accompanied by a verify operation. That is, the flash memory device performs the verify operation in the middle of the program operation to determine whether desired data is properly stored in a memory cell, and performs a read operation only after the desired data is stored in all memory cells.
Ideally, a bit line current I_BL flowing through a bit line BL at the time of the verify operation, through which it is determined that the desired data is stored in the memory cell, is about the same as a bit line current I_BL flowing through the bit line BL at the time of the read operation. However, in actuality, the bit line current I_BL at the time of the verify operation is different from the bit line current I_BL at the time of the read operation due to bouncing of the common source line CSL, back pattern dependency (BPD), interference, temperature and the like.
FIGS. 2 to 5 are diagrams illustrating a change in the bit line current I_BL illustrated in FIG. 1. The bit line selection signal BL_SEL has a voltage level corresponding to ‘V1’ at the time of the precharging operation and has a voltage level corresponding to ‘V2’ lower than ‘V1’ at the time of the verify operation and a writing operation. For convenience, the bit line current I_BL during the verify operation is illustrated as ‘I_BL_VE’ and the bit line current I_BL during the read operation is illustrated as ‘I_BL_RD’.
FIG. 2 is a diagram illustrating variation in the bit line current I_BL_VE during the verify operation and variation in the bit line current I_BL_RD during the read operation in an ideal case. As it can be seen from FIG. 2, the variation in the bit line current I_BL_VE during the verify operation is about the same as the variation in the bit line current I_BL_RD during the read operation.
FIG. 3 is a diagram illustrating variation in the bit line current I_BL_VE during the verify operation and variation in the bit line current I_BL_RD during the read operation when reflecting the bouncing of the common source line CSL. As it can be seen from FIG. 3, the bit line current I_BL_RD during the read operation is higher than the bit line current I_BL_VE during the verify operation. FIG. 4 is a diagram illustrating variation in the bit line current I_BL_VE during the verify operation and variation in the bit line current I_BL_RD during the read operation when reflecting the bouncing of the common source line CSL and the BPD. As it can be seen from FIG. 4, the bit line current I_BL_RD during the read operation is lower than the bit line current I_BL_VE during the verify operation. FIG. 5 is a diagram illustrating variation in the bit line current I_BL_VE during the verify operation and variation in the bit line current I_BL_RD during the read operation when reflecting the interference. Similarly to FIG. 4, as it can be seen from FIG. 5, the bit line current I_BL_RD during the read operation is lower than the bit line current I_BL_VE during the verify operation.
The main reason for the phenomena illustrated in FIGS. 3 to 5 occur is that the amount of the current flowing through the common source line CSL varies depending on the state of data stored in a plurality of memory cells. In other words, when the read operation is performed with respect to two memory cells storing the same data by using the page buffer 130, a change occurs in the amount of the current sunk through the common source line CSL depending on the state of the data stored in the plurality of memory cells.
FIG. 6 is a waveform diagram illustrating a read operation waveform of the flash memory device illustrated in FIG. 1.
Referring to FIG. 6, the flash memory device performs the read operation after the verify operation is completed with respect to all memory cells. The read operation includes a precharging period T1 for precharging a bit line BL, an evaluation period T2 for evaluating the precharged bit line BL, and a sensing period T3 for sensing the voltage level of the bit line BL. In the evaluation period T2, a charge precharged on the bit line BL is sunk to a terminal of the ground supply voltage VSS through the common source line CSL. At this time, a second control signal CTR2 is activated.
As it can be seen from FIG. 6, a change occurs in the bit line current I_BL_RD during the read operation due to the reason explained in FIGS. 3 to 5. The change in the bit line current I_BL_RD during the read operation represents a change in the data distribution of memory cells. As a result, during the read operation, the page buffer 130 may not perform a sensing operation of desired data.